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IS61QDP2B22M18A1 Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc |
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IS61QDP2B22M18A1 Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc |
5 / 33 page IS61QDP2B22M18A/A1/A2 IS61QDP2B21M36A/A1 /A2 Integrated Silicon Solution, Inc.- www.issi.com Rev. B 10/02/2014 5 Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee impedance matching is between 175Ω and 350Ω at V DDQ=1.5V. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF. The ZQ pin can also be directly connected to V DDQ to obtain a minimum impedance setting. ZQ must never be connected to V SS . Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances value. The final impedance value is achieved within 1024 clock cycles. Depth Expansion Separate input and output ports enable easy depth expansion, as each port can be selected and deselected independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending read and write transactions are always completed prior to deselecting the corresponding port. Valid Data Indicator (QVLD) A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle before the final valid read data arrives. Delay Locked Loop (DLL) Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock frequency. Therefore device can have stable output over the temperature and voltage variation. DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL off mode, the device behaves with one clock cycle latency and a longer access time which is known in DDR-I or legacy QUAD mode. The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K# for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being reset, it gets locked after 2048 cycles of stable clock. ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a SRAM to change input resistive termination condition by ODT pin which function can have three status, High, Low, and Floating. Each status can have different ODT termination value |
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