IS61QDPB24M18A/A1/A2

IS61QDPB22M36A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. C

08/21/2014

4

SRAM Features description

Block Diagram

Data

Register

Address

Register

Control

Logic

D (Data-In)

36 (18)

20 (21)

Address

4 (2)

R#

W#

Clock

Generator

Doff#

K

K#

2M x 36

(4M x 18)

Memory Array

Write

Driver

Select Output Control

Output

Register

19 (20)

72 (36)

72 (36)

72 (36)

72 (36)

72 (36)

72(36)

36 (18)

Q (Data-out)

QVLD

CQ, CQ#

(Echo Clocks)

2

36 (18)

QVLD

CQ, CQ#

(Echo Clocks)

2

Read Operations

The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state

at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to

complete the burst of two in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with

timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

The data corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The

data corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock.

A NOP operation (R# is high) does not terminate the previous read.

Write Operations

Write operations can also be initiated at every rising edge of the K clock with first data whenever W# is low. The write

address is provided half cycle with second data later, registered by the rising edge of K#, so the write always occurs in

bursts of two.

The write data is provided in a

n ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is

presented half cycle before the rising edge of the following K clock. The data-in corresponding to the second write

burst address follows next, registered by the rising edge of K#.