8

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00B

04/23/08

IS61WV25632ALL/ALS

IS61WV25632BLL/BLS

IS64WV25632BLL/BLS

-8

-10

Symbol

Parameter

Min. Max.

Min. Max.

Unit

Read Cycle Time

8

—

10

—

ns

Address Access Time

—

8

—

10

ns

Output Hold Time

2.5

—

2.5

—

ns

CE

Access Time

—

8

—

10

ns

OE

Access Time

—

5.5

—

6.5

ns

OE

to High-Z Output

—

3

—

4

ns

OE

to Low-Z Output

0

—

0

—

ns

CE

to High-Z Output

0

3

0

4

ns

CE

to Low-Z Output

3

—

3

—

ns

Byte Enable to Data Valid

—

5.5

—

6.5

ns

Byte Enable to Low-Z

0

—

0

—

ns

Byte Enable to High-Z

0

3

0

3

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.