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ADC1225 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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ADC1225 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 18 page Functional Description (Continued) TABLE II Status Bit Locations and Meanings (Continued) Status Status Condition to Bit Bit Meaning Clear Status Location Bit DB1 EOC ‘‘High’’ indicates that the conversion is completed and data is transferred to the output latch DB0 INT ‘‘High’’ indicates that Data read or it is the end of the status read conversion and the or status data is ready to read write 30 INTERFACE 31 RESET OF INTERRUPT INT goes low at the end of the conversion and indicates that data is transferred to the output latch By reading data INT will be reset to high on the leading edge of the first read (RD going low) INT is also reset on the leading (falling) edge of WR when starting a conversion 32 READY OUT To simplify the hardware connection to high speed micro- processors a READY OUT line is provided This allows the A-to-D to insert a wait state in the mP’s read cycle The equivalent circuit and the timing diagram for READY OUT is shown in Figures 7 and 8 TLH5676 – 9 FIGURE 7 READY OUT Equivalent Circuit TLH5676 – 10 FIGURE 8 READY OUT Timing Diagram 33 RESETTING THE AD All the internal logic can be reset which will abort any con- version in process and reset the status bits The reset func- tion is achieved by performing a status write (CS WR and STATUS are low) 34 ADDITIONAL TIMING AND INTERFACE OPTIONS ADC1225 1 WR and RD can be tied together with CS low continu- ously or strobed The previous conversion’s data will be available when the WR and RD are low as shown below One drawback is that since the conversion is started on the falling edge and the data read on the rising edge of WR RD the first data access will have erroneous information de- pending on the power-up state of the internal output latch- es If the WR RD strobe is longer than the conversion time INTR will never go low to signal the end of a conversion The conversion will be completed and the output latches will be updated In this case the READY OUT signal can be used to sense the end of the conversion since it will go low when the output latches are being updated TLH5676 – 24 FIGURE 9 10 |
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Similar Description - ADC1225 |
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