IS66WVC4M16ALL datasheet(8/67 Pages) ISSI

Part #	IS66WVC4M16ALL

Description	Mixed Mode supports asynchronous write and synchronous read operation

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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IS66WVC4M16ALL

IS67WVC4M16ALL

8

Rev. B | July 2012

www.issi.com – SRAM@issi.com

Bus Operating Modes

CellularRAM products incorporate a burst mode interface targeted at low-power,

wireless applications. This bus interface supports asynchronous, page mode, and burst

mode read and write transfers. The specific interface supported is defined by the value

loaded into the bus configuration register. Page mode is controlled by the refresh configuration

register (RCR[7]).

Burst Mode Operation

Burst mode operations enable high-speed synchronous READ and WRITE operations.

Burst operations consist of a multi-clock sequence that must be performed in an

ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge

of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates

whether the operation is going to be a READ (WE#=HIGH) or WRITE(WE#=LOW).

The size of a burst can be specified in the BCR either as a fixed length or continuous.

Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous

bursts have the ability to start at a specified address and burst to the end of the row.

(Row length of 128 words or 256 words is a manufacturer option.)

The latency count stored in the BCR defines the number of clock cycles that elapse

before the initial data value is transferred between the processor and CellularRAM

device. The initial latency for READ operations can be configured as fixed or variable.

(WRITE operations always use fixed latency). Variable latency allows the CellularRAM to

be configured for minimum latency at high clock frequencies, but the controller must

monitor WAIT to detect any conflict with refresh cycles.(see Figure 26).

Fixed latency outputs the first data word after the worst-case access delay, including

allowance for refresh collisions. The initial latency time and clock speed determine the

latency count setting. Fixed latency is used when the controller cannot monitor WAIT.

Fixed latency also provides improved performance at lower clock frequencies.

The WAIT output asserts when a burst is initiated and de-asserts to indicate when data

is to be transferred into (or out of) the memory. WAIT will again be asserted at the

boundary of the row unless wrapping within the burst length.

To access other devices on the same bus without the timing penalty of the initial latency

for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.

CLK must be stopped LOW. If another device will use the data bus while the burst is

suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,

OE# can remain LOW. Note that the WAIT output will continue to be active, and as a

result no other devices should directly share the WAIT connection to the controller. To

continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is

available on the bus.

CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than

tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE#

should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.

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