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2015-10-0002

PT0455-3

10/20/15

5

PI6ULS5V9515A

I

Functional Description

The PI6ULS5V9515A is a CMOS integrated circuit intended for I

contains two identical bidirectional open-drain buffer circuits that enable I

degradation of system performance.

The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance.,

accommodating more I

buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I

application.

The PI6ULS5V9515A has an EN pin to turn the drivers on and off. This can be used to isolate a badly behaved slave on

power-up until after the system power-up reset. It should never change state during an I

a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I

enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures.

The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower

(0.43V) or even more lower. When the output internally is driven low he low is not recognized as a low by the input.. This

prevents a lockup condition from occurring when the input low condition is released.

Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration.

Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input

and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a

slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515A-type device in series, the

second device does not recognize it as a valid low and will not propagate it as a buffered low again.

The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming

active until Vcc is at a valid level (Vcc = 2.3 V).

As with the standard I

PI6ULS5V9515A has standard open-collector configuration of the I

system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast

mode I

Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

Application Information

A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I

connected to a 5V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.

The PI6ULS5V9515A is 5V tolerant, so it does not require any additional circuitry to translate between different bus voltages.

When one side of the PI6ULS5V9515A is pulled LOW by a device on the I

falling edge and causes the internal driver on the other side to turn on, thus causing the other side to also go LOW. The side driven

Figure 5 and Figure 6 show the waveforms that are seen in a typical application. If the bus master in Figure4 writes to the slave

through the PI6ULS5V9515A, Bus 0 has the waveform shown in Figure 5. This looks like a normal I

falling edge of the eighth clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it low through the

has transmitted the ninth clock pulse, the slave releases the data line.

in the example.

PI6ULS5V9515A and transmitted to Bus 0.