H10

EN1

D10

Charge

(see Note A)

(see Note A)

(see Note A)

(see Note A)

(see Note B)

(see Note B)

(see

Note C)

(see Note D)

(see

Note D)

Pump

VDD

EN2

VBIAS_DQS

VDD

VBIAS

M4

r4

EN_DQS1

M6

r6

M5

r5

EN_DQS2

H

(see Note A)

D

(see Note B)

(see Note C)

EN

(see Note D)

Charge

Pump

M3

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74CBTU4411

SCDS192A – APRIL 2005 – REVISED FEBRUARY 2016

SN74CBTU4411 11-Bit 1-of-4 Multiplexer/Demultiplexer

1.8-V DDR-II Switch With Charge Pump and Precharged Outputs

1

1 Features

1

•

Supports SSTL_18 Signaling Levels

•

Suitable for DDR-II Applications

•

D-Port Outputs are Precharged by Bias Voltage

•

Internal Termination for Control Inputs

•

High Bandwidth (400 MHz Minimum)

•

•

Internal 400-

Ω Pulldown Resistors

•

Low Differential and Rising or Falling Edge Skew

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

2 Applications

•

ATCA Solutions

•

Automated External Defibrillators

•

Adaptive Lighting

•

Blood Gas Analyzers: Portable

•

Bluetooth Headsets

•

CT Scanners

•

Cameras: Surveillance Analog

•

Chemical and Gas Sensors

•

DLP 3D Machine Vision and Optical Networking

3 Description

The SN74CBTU4411 device is a high-bandwidth,

SSTL_18 compatible FET multiplexer/demultiplexer

an internal charge pump to elevate the gate voltage

and supports rail-to-rail signaling on data input/output

(I/O) ports. The device also features very low data I/O

capacitance to minimize capacitive loading and signal

capacitance among channels results in extremely low

differential and rising or falling edge skew. This

allows the device to show optimal performance in

DDR-II applications.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE

SN74CBTU4411ZST

NFBGA (72)

7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic, Each FET Switch (SW1)

A.

Applicable for ports H0 through H9

B.

Applicable for ports D0 through D9

C.

D.

EN is the internal enable signal applied to

the switch.

Simplified Schematic, Each FET Switch (SW2)

A.

EN_DQS1, EN_DQS2, EN1, and EN2 are

the internal enable signals applied to the

switch.

B.

C.

D.