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MB9AF115NA Datasheet(PDF) 8 Page - SPANSION

Part # MB9AF115NA
Description  This document states the current technical specifications regarding
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D a t a S h e e t
December 16, 2014, MB9A110A-DS706-00011-3v0-E
5
CONFIDENTIAL
External Interrupt Controller Unit
 Up to 16 external interrupt input pins.
 Include one non-maskable interrupt (NMI) input pin.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
 Capable of pull-up control per pin
 Capable of reading pin level directly
 Built-in the port relocate function
 Up to 83 fast General Purpose I/O Ports @ 100pin Package
 Some ports are 5V tolerant I/O (MB9AF115MA/NA, MB9AF116MA/NA only)
Please see "PIN DESCRIPTION" to confirm the corresponding pins.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
 Main Clock
: 4MHz to 48MHz
 Sub Clock
: 32.768kHz
 Built-in high-speed CR Clock: 4MHz
 Built-in low-speed CR Clock : 100kHz
 Main PLL Clock
[Resets]
 Reset requests from INITX pins
 Power-on reset
 Software reset
 Watchdog timers reset
 Low-voltage detector reset
 Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
 External clock failure (clock stop) is detected, reset is asserted.
 External frequency anomaly is detected, interrupt or reset is asserted.


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