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MB9AF142LB Datasheet(PDF) 8 Page - SPANSION |
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MB9AF142LB Datasheet(HTML) 8 Page - SPANSION |
8 / 121 page D a t a S h e e t June 10, 2015, MB9A140NB_DS706-00040-4v0-E 5 CONFIDENTIAL Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: 4 MHz to 48 MHz Sub Clock: 32.768 kHz Built-in high-speed CR Clock: 4 MHz Built-in low-speed CR Clock: 100 kHz Main PLL Clock [Resets] Reset requests from INITX pin Power on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. External clock failure (clock stop) is detected, reset is asserted. External frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported. Sleep Timer RTC Stop Deep Standby RTC (selectable between keeping the value of RAM and not) Deep Standby Stop (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM).* *: MB9AF141LB/MB, F142LB/MB and F144LB/MB support only SWJ-DP. Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 1.65 V to 3.6 V |
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