Electronic Components Datasheet Search |
|
MB9AF142NB Datasheet(PDF) 5 Page - SPANSION |
|
MB9AF142NB Datasheet(HTML) 5 Page - SPANSION |
5 / 121 page D a t a S h e e t 2 MB9A140NB_DS706-00040-4v0-E, June 10, 2015 CONFIDENTIAL Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) Work area: 32 Kbytes (lower bank) Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes External Bus Interface* Supports SRAM, NOR Flash memory device Up to 8 chip selects 8-/16-bit Data width Up to 25-bit Address bit Maximum area size : Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function * : MB9AF141LB, F142LB and F144LB do not support External Bus Interface. Multi-function Serial Interface (Max 8channels) 4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3) Operation mode is selectable from the followings for each channel. UART CSIO I 2C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4) Various error detection functions available (parity errors, framing errors, and overrun errors) * : MB9AF141LB, F142LB and F144LB do not support Hardware Flow control. [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [I 2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported |
Similar Part No. - MB9AF142NB |
|
Similar Description - MB9AF142NB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |