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MB9A310K Datasheet(PDF) 9 Page - SPANSION

Part # MB9A310K
Description  This document states the current technical specifications regarding
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D a t a S h e e t
6
MB9A310K-DS706-00029-2v0-E, February 20, 2015
CONFIDENTIAL
 Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
 Main Clock
: 4MHz to 48MHz
 Sub Clock
: 32.768kHz
 High-speed internal CR Clock
: 4MHz
 Low-speed internal CR Clock
: 100kHz
 Main PLL Clock
[Resets]
 Reset requests from INITX pin
 Power on reset
 Software reset
 Watchdog timers reset
 Low-voltage detector reset
 Clock supervisor reset
 Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
 External OSC clock failure (clock stop) is detected, reset is asserted.
 External OSC frequency anomaly is detected, interrupt or reset is asserted.
 Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low Power Consumption Mode
Six Low Power Consumption modes supported.
 SLEEP
 TIMER
 RTC
 STOP
 Deep stand-by RTC
 Deep stand-by STOP
 Debug
Serial Wire JTAG Debug Port (SWJ-DP)
 Power Supply
 Wide range voltage
: VCC
= 2.7V to 5.5V
 Power supply for USB I/O : USBVCC0 = 3.0V to 3.6V (when USB is used)
= 2.7V to 5.5V (when GPIO is used)


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