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MB9BF106RA Datasheet(PDF) 5 Page - SPANSION |
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MB9BF106RA Datasheet(HTML) 5 Page - SPANSION |
5 / 109 page D a t a S h e e t 2 MB9B100A-DS706-00020-2v0-E, December 15, 2014 CONFIDENTIAL FEATURES 32-bit ARM Cortex-M3 Core ・Processor version: r2p0 ・Up to 80MHz Frequency Operation ・Memory Protection Unit (MPU): improve the reliability of an embedded system ・Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels ・24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] ・Up to 512 Kbyte ・Read cycle: 0wait-cycle@up to 60MHz, 2wait-cycle* above *: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle ・Security function for code protection [SRAM] This series contain a total of up to 64Kbyte on-chip SRAM. This is composed of two independent SRAM(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. ・SRAM0: Up to 32 Kbyte ・SRAM1: Up to 32 Kbyte |
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