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MB9B320TA Datasheet(PDF) 5 Page - SPANSION |
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MB9B320TA Datasheet(HTML) 5 Page - SPANSION |
5 / 141 page D a t a S h e e t 2 MB9B320TA_DS706-00062-2v0-E, January 30, 2015 CONFIDENTIAL Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 60 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Main area: Up to 1.5Mbytes(1008Kbytes(ROM0) + 512Kbytes(ROM1) of Upper bank and 16Kbytes(ROM0) of Lower bank.) Work area 64 Kbytes(ROM1) of Lower bank Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 96 Kbytes SRAM1: Up to 96 Kbytes External Bus Interface Supports SRAM, NOR NAND Flash memory device Up to 8 chip selects 8/16-bit Data width Up to 25-bit Address bit Maximum area size : Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function USB Interface The USB interface is composed of Function and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB function] USB2.0 Full-Speed supported Max 6 EndPoint supported EndPoint 0 is control transfer EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer EndPoint 1 to 5 are comprised of Double Buffers. The size of each EndPoint is as follows. EndPoint 0, 2 to 5:64 bytes EndPoint 1: 256 bytes [USB host] USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support USB Device connected/dis-connected automatic detection Automatic processing of the IN/OUT token handshake packet Max 256-byte packet-length supported Wake-up function supported |
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