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CD40174BM Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CD40174BM Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF5987 February 1988 CD40174BMCD40174BC Hex D Flip-Flop CD40175BMCD40175BC Quad D Flip-Flop General Description The CD40174B consists of six positive-edge triggered D-type flip-flops the true outputs from each flip-flop are ex- ternally available The CD40175B consists of four positive- edge triggered D-type flip-flops both the true and comple- ment outputs from each flip-flop are externally available All flip-flops are controlled by a common clock and a com- mon clear Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse The clearing opera- tion enabled by a negative pulse at Clear input clears all Q outputs to logical ‘‘0’’ and Qs (CD40175B only) to logical ‘‘1’’ All inputs are protected from static discharge by diode clamps to VDD and VSS Features Y Wide supply voltage range 3V to 15V Y High noise immunity 045 VDD (typ) Y Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74 LS Y Equivalent to MC14174B MC14175B Y Equivalent to MM74C174 MM74C175 Connection Diagrams CD40174B Dual-In-Line Package TLF5987 – 1 Top View Order Number CD40174B or CD40175B Truth Table Inputs Outputs Clear Clock D Q Q LX X L H H u HH L H u LL H HH X NC NC HL X NC NC H e High level L e Low level X e Irrelevant u e Transition from low to high level NC e No change e Q for CD40175B only CD40175B Dual-In-Line Package TLF5987 – 2 Top View C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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