AD9234-1000EBZ datasheet(1/66 Pages) AD

Part #	AD9234-1000EBZ

Description	12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

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12-Bit, 1 GSPS/500 MSPS JESD204B,

Dual Analog-to-Digital Converter

Data Sheet

AD9234

FEATURES

JESD204B (Subclass 1) coded serial digital outputs

1.5 W total power per channel at 1 GSPS (default settings)

SFDR

79 dBFS at 340 MHz (1 GSPS)

86 dBFS at 340 MHz (500 MSPS)

SNR

63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS)

65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS)

ENOB = 10.4 bits at 10 MHz

DNL = ±0.16 LSB; INL = ±0.35 LSB

Noise density

−151 dBFS/Hz (1 GSPS)

−150 dBFS/Hz (500 MSPS)

1.25 V, 2.5 V, and 3.3 V dc supply operation

Low swing full scale input

1.34 V p-p nominal (1 GSPS)

1.63 V p-p nominal (500 MSPS)

No missing codes

Internal ADC voltage reference

Flexible termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

2 GHz usable analog input full power bandwidth

95 dB channel isolation/crosstalk

Amplitude detect bits for efficient AGC implementation

Differential clock input

Optional decimate-by-2 DDC per channel

Differential clock input

Integer clock divide by 1, 2, 4, or 8

Flexible JESD204B lane configurations

Small signal dither

APPLICATIONS

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

Point-to-point radio systems

Digital predistortion observation path

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation (spectrum analyzers, network analyzers,

integrated RF test solutions)

Digital oscilloscopes

High speed data acquisition systems

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

PRODUCT HIGHLIGHTS

1. Low power consumption analog core, 12-bit, 1.0 GSPS dual

analog-to-digital converter (ADC) with 1.5 W per channel.

2. Wide full power bandwidth supports IF sampling of signals

up to 2 GHz.

3. Buffered inputs with programmable input termination

eases filter design and implementation.

4. Flexible serial port interface (SPI) controls various product

features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 9 mm × 9 mm 64-lead LFCSP.

7. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS

dual ADC.

VIN+A

VIN–A

VIN+B

VIN–B

CLK+

CLK–

AD9234

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

÷2

÷4

SYSREF±

CLOCK

GENERATION

AND ADJUST

12

PDWN/

STBY

SYNCINB±

FD_A

FD_B

BUFFER

JESD204B

SUBCLASS 1

CONTROL

V_1P0

÷8

FAST

DETECT

AGND

DRGND DGND SDIO SCLK CSB

AVDD1

(1.25V)

AVDD2

(2.5V)

AVDD3

(3.3V)

AVDD1_SR

(1.25V)

DVDD

(1.25V)

DRVDD

(1.25V)

SPIVDD

(1.8V TO 3.3V)

4

SIGNAL

MONITOR

ADC

CORE

ADC

CORE

SPI CONTROL

DECIMATE

BY 2

DECIMATE

BY 2

SIGNAL

MONITOR

Rev. A

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Tel: 781.329.4700

Technical Support

www.analog.com

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