Data Sheet

ADN4650/ADN4651/ADN4652

Rev. B | Page 5 of 24

Timing Diagram

>1.3V

1.2V

0V

0V

~1.3V

~1.0V

~ +0.3V

~ –0.3V

<1.1V

+0.1V

+0.1V

+0.1V

–0.1V

Figure 4. Fail-Safe Timing Diagram

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.

Table 4.

Parameter

Symbol

Value

Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

5000

V rms

1-minute duration

Minimum External Air Gap (Clearance)

L (I01)

7.8

mm min

Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage)

L (I02)

7.8

mm min

Measured from input terminals to output terminals,

shortest distance path along body

Minimum Clearance in the Plane of the Printed

Circuit Board (PCB Clearance)

L (PCB)

8.1

mm min

Measured from input terminals to output terminals,

shortest distance through air, line of sight, in the PCB

mounting plane

Minimum Internal Gap (Internal Clearance)

17

µm min

Insulation distance through insulation

Tracking Resistance (Comparative Tracking Index)

CTI

>400

V

DIN IEC 112/VDE 0303 Part 1

Material Group

II

Material Group (DIN VDE 0110, 1/89, Table 1)

PACKAGE CHARACTERISTICS

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Ω

2.2

pF

f = 1 MHz

3.7

pF

IC Junction to Ambient Thermal Resistance

45.7

°C/W

Thermal simulation with 4-layer standard JEDEC PCB

1

The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.

2

Input capacitance is from any input data pin to ground.