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ADuM4153BRIZ-RL Datasheet(PDF) 7 Page - Analog Devices

Part # ADuM4153BRIZ-RL
Description  5 kV, 7-Channel, SPIsolator Digital Isolators for SPI
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADuM4153BRIZ-RL Datasheet(HTML) 7 Page - Analog Devices

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Data Sheet
ADuM4151/ADuM4152/ADuM4153
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.
Table 7. Switching Specifications
Parameter
Symbol
A Grade
B Grade
Unit
Test Conditions/Comments
Min
Typ
Max
Min
Typ
Max
MCLK, MO, SO
SPI Clock Rate
SPIMCLK
1
15.6
MHz
1/(4 × tPHL)
Data Rate Fast (MO, SO)
DRFAST
2
34
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
27
16
ns
50% input to 50% output
Pulse Width
PW
100
12.5
ns
Within PWD limit
Pulse Width Distortion
PWD
3
3
ns
|tPLH − tPHL|
Codirectional Channel Matching1
tPSKCD
3
2
ns
Jitter, High Speed
JHS
1
1
ns
MSS
Data Rate Fast
DRFAST
2
34
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
27
26
ns
50% input to 50% output
Pulse Width
PW
100
12.5
ns
Within PWD limit
Pulse Width Distortion
PWD
3
3
ns
|tPLH − tPHL|
Setup Time2
MSSSETUP
1.5
10
ns
Jitter, High Speed
JHS
1
1
ns
VIA, VIB, VIC
Data Rate Slow
DRSLOW
250
250
kbps
Within PWD limit
Propagation Delay
tPHL, tPLH
0.1
2.6
0.1
2.6
µs
50% input to 50% output
Pulse Width
PW
4
4
µs
Within PWD limit
Jitter, Low Speed
JLS
2.5
2.5
µs
VIx3 Minimum Input Skew4
tVIx SKEW3
10
10
ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
VIx = VIA, VIB, or VIC.
4
An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 8. Supply Current
Device Number
Symbol
1 MHz, A Grade/B Grade
17 MHz, B Grade
Unit
Test Conditions/Comments
Min
Typ
Max
Min
Typ
Max
ADuM4151
IDD1
4.0
8.5
13.9
22
mA
CL = 0 pF, low speed channels
IDD2
4.6
8
9.0
17
mA
CL = 0 pF, low speed channels
ADuM4152
IDD1
4.8
8.5
14.0
21.5
mA
CL = 0 pF, low speed channels
IDD2
5.0
8
10.0
16
mA
CL = 0 pF, low speed channels
ADuM4153
IDD1
4.0
8.5
14.0
22
mA
CL = 0 pF, low speed channels
IDD2
4.7
9
10.0
15
mA
CL = 0 pF, low speed channels
Rev. A | Page 7 of 22


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