4 / 15 page  CY7C1351F Document #: 38-05210 Rev. *B Page 4 of 15 CE3 92 B6 Input- Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 andCE2 to select/deselect the device. OE 86 F4 Input- Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN 87 M4 Input- Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previ- ous cycle when required. ZZ 64 T7 Input- Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity pre- served. During normal operation, this pin can be connected to Vss or left floating. DQs 52,53,56,57,58, 59,62,63,68,69, 72,73,74,75,78, 79,2,3,6,7,8,9, 12,13,18,19,22, 23,24,25,28,29 K6,L6,M6,N6, K7,L7,N7,P7, E6,F6,G6,H6, D7,E7,G7,H7, D1,E1,G1,H1, E2,F2,G2,H2, K1,L1,N1,P1, K2,L2,M2,N2 I/O- Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory loca- tion specified by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a three-state condition. The outputs are automatically three-stat- ed during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQP[A:D] 51,80,1,30 P6,D6,D2,P2 I/O- Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:D] is con- trolled by BW[A:D] correspondingly. MODE 31 R3 Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD 15,41,65,91 J2,C4,J4,R4, J6 Power Supply Power supply inputs to the core of the device. VDDQ 4,11,20,27,54, 61,70,77 A1,F1,J1,M1, U1,A7,F7,J7, M7,U7 I/O Power Sup- ply Power supply for the I/O circuitry. VSS 5,10,17,21,26, 40,55,60,67,71, 76,90, D3,E3,F3,H3, J3,K3,M3,N3, P3,D5,E5,F5, H5,J5,K5,M5, N5,P5 Ground Ground for the device. NC 14,16,38,39,42, 43,66,83,84 B1,C1,R1,T1, T2,U2,U3,A4, D4,G4,L4,U4, U5,T6,U6,B7, C7,R5,R7,T7 – No Connects. Not Internally connected to the die. Pin Definitions Name TQFP BGA I/O Description |
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