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PEEL18CV8T-7 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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PEEL18CV8T-7 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 10 page 7 04-02-004H International CMOS Technology ® PEELTM 18CV8 8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (Unless otherwise specified). 9. Test one output at a time for a duration of less than 1 second. 10. ICC for a typical application: This parameter is tested with the device programmed as an 8-bit Counter. 11. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. 12. Available only for 18CV8 -15/I-15/-25/I-25 grades 13. 24mA available for 18CV8-5/-7. All other speeds are 16mA. A.C. Electrical Characteristics Over the operating range 8 Switching Waveforms Notes: 1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than 20 ns. 2. VI and VO are not specified for program/verify operation. 3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels. 4. I/O pins are 0V and VCC. 5. “Input” refers to an input pin signal. 6. tOE is measured from input transition to VREF±0.1V, TOD is measured from input transition to VOH-0.1V or VOL+0.1V; VREF=VL. 7. Capacitances are tested on a sample basis. Symbol Parameter -5 -7 -10/I-10 -15/I-15 -25/I-25 Units Min Max Min Max Min Max Min Max Min Max tPD Input5 to non-registered output 5 7.5 10 15 25 ns tOE Input5 to output enable6 5 7.5 10 15 25 ns tOD Input5 to output disable6 5 7.5 10 15 25 ns tCO1 Clock to Output 4 7 7 12 15 ns tCO2 Clock to comb. output delay via internal registered feedback 7.5 10 12 25 35 ns tCF Clock to Feedback 2.5 3.5 4 8 15 ns tSC Input5 or feedback setup to clock 3.5 5 51220 ns tHC Input5 hold after clock 00 00 0 ns tCL, tCH Clock low time, clock high time8 3 3.5 51015 ns tCP Min clock period Ext (tSC + tCO1) 7 12 12 24 35 ns fMAX1 Internal feedback (1/tSC+tCF)11 166.7 117.6 111 50 28.5 MHz fMAX2 External Feedback (1/tCP)11 133 83.3 83.3 41.6 28.5 MHz fMAX3 No Feedback (1/tCL+tCH)11 166.7 142.8 100 50 33.3 MHz tAW Asynchronous Reset Pulse Width 5 7.5 10 15 25 ns tAP Input 5 to Asynchronous Reset 5 7.5 10 15 25 ns tAR Asynchronous Reset recovery time 5 7.5 10 15 25 ns tRESET Power-on reset time for registers in clear state 555 5 5 µs Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs |
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