9

04-02-051B

Figure 15. Sequential Timing – Waveforms and Block Diagram

Notes

1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V

for periods less than 20ns.

10% and 90% levels.

4. Test one output at a time for a duration of less than 1 sec.

5. Capacitances are tested on a sample basis.

6. Test conditions assume: signal transition times of 5ns or less from the

10% and 90% points, timing reference levels of 1.5V (unless

otherwise specified).

8. DIP: “System-clock” refers to pin 1/13 high speed clocks. PLCC: “Sys-

tem-clock” refers to pin 2/16 high speed clocks.

9. For T or JK registers in toggle (divide by 2) operation only.

10. For combinatorial and async-clock to LCC output delay.

11. ICC for a typical application: This parameter is tested with the device

programmed as a 10-bit D-type counter.

12. Test loads are specified in Section 5 of the Data Book.

13. “Async. Clock” refers to the clock from the Sum term (OR gate).

14. The “LCC” term indicates that the timing parameter is applied to the

LCC register. The “LCC/IOC” term indicates that the timing

parameter is applied to both the LCC and IOC registers.

16. The term “input” without any reference to another term refers to an

(external) input pin.

is always slower than the data from the pin or input by the absolute

from the pin or input is required, i.e. the external data and clock can

be sent to the device simultaneously. Additionally, the data from the

arrive at the IOC register.

5V