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UCC37324 Datasheet(PDF) 9 Page - Texas Instruments |
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UCC37324 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 15 page UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 9 www.ti.com APPLICATION INFORMATION operational waveforms and circuit layout Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load. The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. Figure 5. In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections should also be made with a small enclosed loop area to minimize the inductance. VDD Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg x f, where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1- µF ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1- µF) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. |
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