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M12L16161A-7T Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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M12L16161A-7T Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
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1 / 27 page  M12L16161A Elite Semiconductor Memory Technology Inc. P.1 Publication Date : Jan. 2000 Revision : 1.3u 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z All inputs are sampled at the positive going edge of the system clock z Burst Read Single-bit Write operation z DQM for masking z Auto & self refresh z 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M12L16161A is 16,777,216 bits synchro- nous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchro- nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating fre- quencies, programmable burst length and pro- grammable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. MAX Freq. Interface Package M12L16161A-4.3T 233MHz M12L16161A-5T 200MHz M12L16161A-5.5T 183MHz M12L16161A-6T 166MHz M12L16161A-7T 143MHz M12L16161A-8T 125MHz LVTTL 50 TSOP(II) PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) |
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