than one volt. Single-ended ECL, Figure 5C, maintains

this desired maximum differential input voltage. TTL

circuit of figure 5D will ensure the voltage applied

between the bases of Q1 and Q2 does not cause

excessive switching delays in the CLC411. Under the

above proscribed four-transistor interface, all variations

were evaluated with approximately 1ns rise and fall

times which produced switching speeds equivalent to

the rated disable/enable switching times found in the

"CLC411 Electrical Characteristics" table.

A general multiplexer configuration using several

CLC411s is illustrated in figure 6, where a typical 8-to-

1 digital mux is used to control the switching operation

of the paralleled CLC411s. Since "break-before-make"

is a guaranteed specification of the CLC411 this

configuration works nicely. Notice the buffers used in

driving the disable pins of the CLC411s. These buffers

may be 15V CMOS logic devices mentioned previously

or any variation of the four-transistor comparator

illustrated above.

As can be seen in Figure 3, the magnitude of the internal

range) and VO (output voltage range, no load) are

specified under these conditions. These parameters

implicitly have 0V as their midpoint, i.e. the VO range

is ±6V, centered at 0V.

the range of the input/output voltages. For example, if

intersecting the other lines in the graph. The circuit

voltages are the ordinates of these intersections. For

this example these points are shown in the graph as

reference voltages are applied, the range for VO is -3V

between the minimum and maximum voltages is

constant, i.e. 12V for VO, only the midpoint has been

(or bypassed to reduce high-frequency noise). The

shifting voltage can be applied to only one of the

reference pins, not both. If extended operation were

needed in the negative direction, Figure 4 may be used

by changing the signs, and applying the resultant

shifts of input/output voltage range.

Printed Circuit Layout & Evaluation Board

Refer to application note OA-15, “Frequent Faux Pas in

Applying Wideband Current Feedback Amplifiers,” for

board layout guidelines and construction techniques. Two

very important points to consider before creating a layout

which are found in the above application note are worth

reiteration. First the input and output pins are sensitive to

parasitic capacitances. These parasitic capacitances

can cause frequency-response peaking or sustained

oscillation. To minimize the adverse effect of parasitic

capacitances, the ground plane should be removed from

those pins to a distance of at least 0.25" Second, leads

should be kept as short as possible in the finished layout.

In particular, the feedback resistor should have its shortest

lead on the inverting input side of the CLC411. The output

is less sensitive to parasitic capacitance and therefore

can drive the longer of the two feedback resistor

connections. The evaluation board available for the CLC411

(part #730013 for through-hole packages, 730027 for SO-

8) may be used as a reference for proper board layout.

Application schematics for this evaluation board are in the

product accessories section of the Comlinear databook.

51015

-10

-5

20

15

10

5

-5

-10

-15

+V

+V

r

+VO

max

-VO

min

V

cm

+

V

cm

_

-V

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