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CLC411AJE Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CLC411AJE Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page N CLC411 High-Speed Video Op Amp with Disable General Description The CLC411 combines a state-of-the-art complementary bipolar process with National’s patented current-feedback architecture to provide a very high-speed op amp operating from ±15V supplies. Drawing only 11mA quiescent current, the CLC411 provides a 200MHz small signal bandwidth and a 2300V/ µs slew rate while delivering a continuous 70mA current output with ±4.5V output swing. The CLC411’s high-speed performance includes a 15ns settling time to 0.1% (2V step) and a 2.3ns rise and fall time (6V step). The CLC411 is designed to meet the requirements of professional broadcast video systems including composite video and high definition television. The CLC411 exceeds the HDTV standard for gain flatness to 30MHz with it's ±0.05dB flat frequency response and exceeds composite video standards with its very low differential gain and phase errors of 0.02%, 0.03°. The CLC411 is the op amp of choice for all video systems requiring upward compatibility from NTSC and PAL to HDTV. The CLC411 features a very fast disable/enable (10ns/55ns) allowing the multiplexing of high-speed signals onto an analog bus through the common output connections of multiple CLC411’s. Using the same signal source to drive disable/enable pins is easy since “break- before-make” is guaranteed. The CLC411 is available in several versions: CLC411AJP -40°C to +85°C 8-pin plastic DIP CLC411AJE -40°C to +85°C 8-pin plastic SOIC CLC411A8B -55°C to +125°C 8-pin hermetic CERDIP, MIL-STD-883 CLC411AMC -55°C to +125°C dice, MIL-STD-883, Level B DESC SMD number: 5962-94566 June 1999 Features s 200MHz small signal bandwidth (1V pp) s ±0.05dB gain flatness to 30MHz s 0.02%, 0.03° differential gain, phase s 2300V/ µs slew rate s 10ns disable to high-impedance output s 70mA continuous output current s ±4.5V output swing into 100 Ω load s ±4.0V input voltage range Applications s HDTV amplifier s Video line driver s High-speed analog bus driver s Video signal multiplexer s DAC output buffer Pinout DIP & SOIC 0.01 µF 0.1 µF 0.1 µF 6.8 µF 6.8 µF 0.01 µF +V r -V r V in + _ 3 2 4 7 8 1 5 6 CLC411 25 Ω R T R g Select R T to yield R in =R T||R g R f V out DIS -V cc +V cc Recommended Inverting Gain Configuration 0 Frequency (5MHz/div) 50 Gain Flatness (Av=+2) - + 1 2 3 4 DIS +Vcc Vout -Vr +Vr Vinv Vnon-inv -Vcc 8 7 6 5 © 1999 National SemiconductorCorporation http://www.national.com Printed in the U.S.A. |
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