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CLC436 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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CLC436 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 6 page  CLC436 Typical Performance Characteristics (Vcc = ±15V, Av = +2, R f = 499W, RL = 1kW; unless specified) CLC436 OPERATION Description The CLC436 is a unity gain stable voltage feedback amplifier. The voltage feedback topology allows for capacitors and nonlinear devices in the feedback path. The matched input bias currents track well over temperature. This allows the DC offset to be minimized by matching the impedance seen by both inputs. The low cost, low power, conventional topology, and high output current make the CLC436 an excellent choice for applications such as: • Low Power Cable Drivers • Active Filters • Buffers • NTSC and PAL Video Systems Gain The non-inverting and inverting gain equations for the CLC436 are as follows: Non-inverting Gain: Inverting Gain: Where Rf is the feedback resistor and Rg is the gain setting resistor. Figure 1 shows the general non- inverting gain configuration including the recommended bypass capacitors. Figure 1: Recommended Non-Inverting Gain Circuit Output Drive Performance The CLC436 can source over 120mA of output current. It can easily drive 9Vpp into a 50Ω load. The circuit shown in Figure 1 demonstrates the output current capability of the CLC436. The circuit values listed below, a 3Vpp input signal and ±15V supplies, were used to obtain the result shown in Figure 2. • Rf = 499Ω • RL = 50Ω • Rg = 249.5Ω • Rin = 50Ω Figure 2: Large Signal Pulse Response into 50 W The high output drive capability of the CLC436 is suitable for driving capacitive loads. When driving a capacitive load or coaxial cable, include a series resistance Rs to improve stability. Refer to the Rs vs Capacitive Load plot in the typical performance section to determine the recommended resistance for various capacitive loads. Single Supply Operation The CLC436 can be operated from a single supply using the topology shown in Figure 3. R1 and R2 form a voltage divider that sets the non-inverting input DC voltage. The coupling capacitor C1 isolates the DC bias point from the previous stage. The DC gain of this circuit is 1 and the high frequency gain is set by Rf and Rg. Power Derating Curves Ambient Temperature ( °C) 20 60 100 0 40 80 120 0 0.2 0.4 0.6 0.8 1.0 140 160 180 AJP AJE IBI, IOS, VIO vs. Temperature Temperature ( °C) 0 -40 20 80 VIO 0 0.5 0.2 1.0 0.4 1.5 0.6 2.0 0.8 2.5 1.0 3.0 1.2 -20 0 40 60 IBI IOS IBI & IOS vs. Common Mode Input Voltage Common Mode Input Voltage 80 -10 -5 0 5 10 0 100 0.5 120 1.0 140 1.5 160 2.0 180 2.5 IBI IOS + - CLC436 Rf 0.1 µF 6.8 µF Vo Vin +Vcc 0.1 µF 6.8 µF -Vcc RL Rg Rin gp Time (100ns/div) -5 -100 -4 -80 -3 -60 -2 -40 -1 -20 0 0 1 20 2 40 3 60 4 80 5 100 Vin = 3Vpp Vout = 9Vpp 1 R R f g + − R R f g http://www.national.com 4 |
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