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178021501 Datasheet(PDF) 7 Page - Wurth Elektronik GmbH & Co. KG, Germany. |
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178021501 Datasheet(HTML) 7 Page - Wurth Elektronik GmbH & Co. KG, Germany. |
7 / 46 page we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 7/46 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module SYMBOL PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT Transient Response TTR Transient response Recovery time 1A/µs load step from 50 to 100%, - 400 - µs VTR Transient response VOUT over/undershoot 1A/µs load step from 50 to 100%, - 90 - mV Quiescent current IQ Input quiescent current EN = 0V, TA = 25°C, 3.5V ≤ VIN ≤ 60V 1.3 4 µA Non switching: VFB = 0.83V, TA = 25°C, VIN = 12 V 200 µA RELIABILITY SYMBOL PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT MTBF Mean Time Between Failures Confidence level 60%, TA=55°C, Activation energy 0.7eV, 1000 hrs test duration, 46185 samples, 1 fail 1.79·109 h NOTES (1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. (2) Typical numbers are valid at 25°C ambient temperature and represent statistically the utmost probability assuming the Gaussian distribution. (3) Depending on heat sink design, number of PCB layers, copper thickness and air flow. (4) Measured on a 100 x 100mm four layer board, with 35µm (1 ounce) copper, no air flow (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. (7) The stated limit of the feedback voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor RSET INT. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor. (8) Value when no voltage divider is present at the EN/UVLO pin. |
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