NB3H60113G

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2

BLOCK DIAGRAM

Clock Buffer/

Crystal

Oscillator and

Phase

Detector

Charge

Pump

VCO

CMOS /

Diff

buffer

CMOS/

Diff

buffer

Feedback

Divider

XIN/CLKIN

XOUT

Crystal

CLK1

CLK2

CLK0

VDD

GND

Output

Divider

Output

Divider

Output

Divider

Configuration

Memory

PLL Block

Frequency

and SS

PD#

Output control

Crystal/Clock Control

PLL Bypass Mode

Figure 1. Simplified Block Diagram

AGC

CMOS

buffer

Notes:

1. CLK0 and CLK1 can be configured to be one of LVPECL, LVDS, HCSL or CML output, or two single−ended LVCMOS/ LVTTL outputs.

2. Dotted lines are the programmable control signals to internal IC blocks.

3. PD# has internal pull down resistor.

PIN FUNCTION DESCRIPTION

NB3H60113G

3

4

1

2

6

5

8

7

XIN/CLKIN

XOUT

PD#

GND

CLK0

CLK1

VDD

CLK2

Figure 2. Pin Connections (Top View) – WDFN8