FM24V01A

Document Number: 001-90869 Rev. *H

Page 6 of 19

High Speed Mode (Hs-mode)

The FM24V01A supports a 3.4-MHz high-speed mode. A master code (00001XXXb) must be issued to place the device into the

high-speed mode. Communication between master and slave will then be enabled for speeds up to 3.4 MHz. A STOP condition will

exit Hs-mode. Single- and multiple-byte reads and writes are supported.

Slave Device Address

The first byte that the FM24V01A expects after a START

condition is the slave address. As shown in Figure 7, the slave

address contains the device type or slave ID, the device select

address bits, and a bit that specifies if the transaction is a read

or a write.

Bits 7-4 are the device type (slave ID) and should be set to 1010b

for the FM24V01A. These bits allow other function types to

reside on the two-wire bus within an identical address range. Bits

3-1 are the device select address bits. They must match the

corresponding value on the external address pins to select the

device. Up to eight FM24V01A devices can reside on the same

two-wire bus by assigning a different address to each. Bit 0 is the

read/write bit (R/W). R/W = ‘1’ indicates a read operation and

R/W = ‘0’ indicates a write operation.

Addressing Overview

After the FM24V01A (as receiver) acknowledges the slave

address, the master can place the memory address on the bus

for a write operation. The address requires two bytes. The

complete 14-bit address is latched internally. Each access

causes the latched address value to be incremented automati-

cally. The current address is the value that is held in the latch;

either a newly written value or the address following the last

access. The current address will be held for as long as power

remains or until a new value is written. Reads always use the

current address. A random read address can be loaded by

beginning a write operation as explained below.

After transmission of each data byte, just prior to the

acknowledge, the FM24V01A increments the internal address

latch. This allows the next sequential byte to be accessed with

no additional addressing. After the last address (3FFFh) is

reached, the address latch will roll over to 0000h. There is no

limit to the number of bytes that can be accessed with a single

read or write operation.

Data Transfer

After the address bytes have been transmitted, data transfer

between the bus master and the FM24V01A can begin. For a

read operation the FM24V01A will place 8 data bits on the bus

then wait for an acknowledge from the master. If the

acknowledge occurs, the FM24V01A will transfer the next

sequential byte. If the acknowledge is not sent, the FM24V01A

will end the read operation. For a write operation, the FM24V01A

will accept 8 data bits from the master then sends an

acknowledge. All data transfer occurs MSB (most significant bit)

first.

Memory Operation

The FM24V01A is designed to operate in a manner very similar

to other two-wire interface memory products. The major differ-

ences result from the higher performance write capability of

F-RAM technology. These improvements result in some differ-

ences between the FM24V01A and a similar configuration

EEPROM during writes. The complete operation for both writes

and reads is explained in the following sections.

Write Operation

All writes begin with a slave address, then a memory address.

The bus master indicates a write operation by setting the LSB of

the slave address (R/W bit) to a '0'. After addressing, the bus

master sends each byte of data to the memory and the memory

generates an acknowledge condition. Any number of sequential

bytes may be written. If the end of the address range is reached

internally, the address counter will wrap from 3FFFh to 0000h.

Unlike other nonvolatile memory technologies, there is no

effective write delay with F-RAM. Since the read and write

access times of the underlying memory are the same, the user

experiences no delay through the bus. The entire memory cycle

occurs in less time than a single bus clock. Therefore, any

operation including read or write can occur immediately following

a write. Acknowledge polling, a technique used with EEPROMs

to determine if a write is complete is unnecessary and will always

return a ready condition.

Figure 6. Data Transfer Format in Hs-Mode

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F/S-mode

Hs-mode

F/S-mode

01

/

A

1

DATA

n (bytes

+ack.)

W

/

R

S

MASTER CODE

S

SLAVE ADD.

Hs-mode continues

S

SLAVE ADD.

P

No Acknowledge

Acknowledge or

No Acknowledge

Figure 7. Memory Slave Device Address

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R/W

LSB

MSB

Slave ID

10

1

0

A2

A0

A1

Device Select