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S6E1B34E0AGV20000 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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S6E1B34E0AGV20000 Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 115 page  Document Number: 001-99224 Rev.** Page 3 of 115 S6E1B3 Series PRELIMINARY active in any low-power consumption modes except RTC, Stop, Deep standby RTC and Deep standby Stop mode. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 HDMI-CEC/Remote Control Receiver (Up to 2 Channels) HDMI-CEC transmitter Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) HDMI-CEC receiver Automatic ACK reply function available Line error detection function available Remote control receiver 4 bytes reception buffer Repeat code detection function available Smart Card Interface Compliant with ISO7816-3 specification Card Reader only/B class card only Available protocols Transmitter: 8E2, 8O2, 8N2 Receiver: 8E1, 8O1, 8N2, 8N1, 9N1 Inverse mode TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes) Clock and Reset Clocks A clock can be selected from five clock sources (two external oscillators, two built-in CR oscillator, and main PLL). Main clock: 4 MHz to 40 MHz Sub clock: 32.768 kHz Built-in high-speed CR clock: 4 MHz Built-in low-speed CR clock: 100 kHz Main PLL clock Resets Reset request from the INITX pin Power on reset Software reset Watchdog timer reset Low-voltage detection reset Clock supervisor reset Clock Supervisor (CSV) The Clock Supervisor monitors the failure of external clocks with a clock generated by a built-in CR oscillator. If an external clock failure (clock stop) is detected, a reset is asserted. If an external frequency anomaly is detected, an interrupt or a reset is asserted. Low-Voltage Detector (LVD) This series monitors the voltage on the VCC pin with a 2-stage mechanism. When the voltage falls below a designated voltage, the Low-voltage Detector generates an interrupt or a reset. LVDR: monitor V CC and auto-reset operation LVD1: monitor V CC and error reporting via an interrupt LVD2: selectable to monitor V CC or LVDI and error reporting via an interrupt Low Power Consumption Mode This series has six low power consumption modes. Sleep Timer RTC Stop Deep standby RTC (selectable between keeping the value of RAM and not) Deep standby Stop (selectable between keeping the value of RAM and not) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent VBAT pin. RTC (calendar circuit) / 32 kHz oscillation circuit. The following circuit can also be used. RTC 32 kHz oscillation circuit Power-on circuit Back up register: 32 bytes Port circuit Debug Serial Wire Debug Port (SW-DP) Micro Trace Buffer (MTB) Unique ID A 41-bit unique value of the device has been set. |
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Similar Description - S6E1B34E0AGV20000 |
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