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7C187-20 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # 7C187-20
Description  64K x 1 Static RAM
Download  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

7C187-20 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C187
Document #: 38-05044 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
(R1 255
Ω MIL)
(R1 255
Ω MIL)
(480
Ω MIL)
(480
Ω MIL)
3.0V
5V
OUTPUT
R1 329
R2 202
30 pF
GND
90%
90%
10%
≤ 5ns
≤ 5 ns
5V
OUTPUT
C187–4
R2 202
5 pF
C187–5
(a)
(b)
OUTPUT
1.73V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1 329
Equivalent to:
THÉVENIN EQUIVALENT
10%
OUTPUT
1.90V
Military
Commercial
ALL INPUT PULSES
167
125
Switching Characteristics Over the Operating Range[6]
7C187-15
7C187-20
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
20
ns
tAA
Address to Data Valid
15
20
ns
tOHA
Output Hold from Address Change
3
5
ns
tACE
CE LOW to Data Valid
15
20
ns
tLZCE
CE LOW to Low Z[7]
3
5
ns
tHZCE
CE HIGH to High Z[7, 8]
8
8
ns
tPU
CE LOW to Power Up
0
0
ns
tPD
CE HIGH to Power Down
15
20
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
15
20
ns
tSCE
CE LOW to Write End
12
15
ns
tAW
Address Set-Up to Write End
12
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
12
15
ns
tSD
Data Set-Up to Write End
10
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z
5
5
ns
tHZWE
WE LOW to High Z[8]
7
7
ns
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7.
At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
8.
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.


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