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CLC532AJP Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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CLC532AJP Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page PARAMETER1 CONDITIONS TYP MAX/MIN RATINGS2 UNITS SYMBOL Case Temperature CLC532AJP/AJE/AIB +25°C -40°C +25°C +85°C FREQUENCY DOMAIN PERFORMANCE -3dB bandwidth V OUT<0.1Vpp 190 140 140 110 MHz SSBW -3dB bandwidth V OUT=2Vpp 45 35 35 30 MHz LSBW gain flatness V OUT<0.1Vpp peaking 0.1MHz to 200MHz 0.2 0.7 0.7 0.8 dB GFP rolloff 0.1MHz to 100MHz 1.0 1.8 1.8 2.6 dB GFR linear phase deviation dc to 100MHz 2.0 deg LPD differential gain C COMP = 5pF; RL=150Ω 0.05 % DG differential phase C COMP = 5pF; RL=150Ω 0.01 deg DP crosstalk rejection 2Vpp, 10MHz 80 75 75 74 dB CT10 2Vpp, 20MHz 74 69 69 68 dB CT20 2Vpp, 30MHz 68 63 63 62 dB CT30 TIME DOMAIN PERFORMANCE rise and fall time 0.5V step 2.7 3.3 3.3 3.8 ns TRS 2V step 10 12.5 12.5 14.5 ns TRL settling time 2V step; from 50% V OUT ±0.0025% 35 ns TS14 ±0.01% 17 24 24 27 ns TSP ±0.1% 13 18 18 21 ns TSS overshoot 2.0V step 2 5 5 6 % OS slew rate 160 130 130 110 V/ µsSR SWITCH PERFORMANCE channel to channel switching time 50% SELECT to 10%V OUT 5 7 7 8 ns SWT10 (2V step at output) 50% SELECT to 90%V OUT 15 20 20 23 ns SWT90 switching transient 30 mV ST DISTORTION AND NOISE PERFORMANCE 2nd harmonic distortion 2Vpp, 5MHz 80 67 67 67 dBc HD2 3rd harmonic distortion 2Vpp, 5MHz 86 68 68 68 dBc HD3 equivalent input noise spot noise voltage >1MHz 3.1 nV/ √Hz SNF integrated noise 1MHz to 100MHz 32 42 42 46 µVrms INV spot noise current 3 pA/ √Hz SNC STATIC AND DC PERFORMANCE * analog output offset voltage 1 6.5 3.5 5.5 mV VOS temperature coefficient 15 90 20 µV/°C DVIO analog output offset voltage matching TBD mV VOSM * analog input bias current 50 250 120 120 µA IBN temperature coefficient 0.3 2.0 0.8 µA/°C DIBN analog input bias current matching TBD µA IBNM analog input resistance 200 90 120 120 k Ω RIN analog input capacitance 2 3.0 2.5 2.5 pF CIN * gain accuracy ±2V 0.998 0.988 0.988 0.988 V/V GA gain matching ±2V TBD V/V GAM integral endpoint non-linearity ±1V (full scale) 0.02 0.05 0.03 0.03 %FS ILIN output voltage no load ±3.4 2.4 2.8 2.8 V VO output current 45 20 30 30 mA IO output resistance dc 1.5 4.0 2.5 2.5 Ω RO DIGITAL INPUT PERFORMANCE ECL mode (pin 6 floating) input voltage logic HIGH -1.1 -1.1 -1.1 V VIH1 input voltage logic LOW -1.5 -1.5 -1.5 V VIL1 input current logic HIGH 14 50 30 30 µA IIH1 input current logic LOW 50 270 110 110 µA IIL1 TTL mode (pin 6 = +5V) input voltage logic HIGH 2.0 2.0 2.0 V VIH2 input voltage logic LOW 0.8 0.8 0.8 V VIL2 input current logic HIGH 14 50 30 30 µA IIH2 input current logic LOW 50 270 110 110 µA IIL2 POWER REQUIREMENTS * supply current (+V CC = +5.0V) no load 23 30 28 25 mA ICC * supply current (-V EE = -5.2V) no load 24 31 30 26 mA IEE nominal power dissipation no load 240 mW PD * power supply rejection ratio 73 60 64 64 dB PSRR Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Electrical Characteristics (+V CC=+5.0V; -VEE=-5.2V; RIN=50Ω Ω Ω Ω Ω; R L=500Ω Ω Ω Ω Ω; C COMP=10pF; ECL Mode, pin 6 = NC) http://www.national.com 2 |
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