64K x 1 Static RAM
CY7C187
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05044 Rev. **
Revised August 24, 2001
87
Features
• High speed
—15 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 220 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C187 is a high-performance CMOS static RAM orga-
nized as 65,536 words x 1 bit. Easy memory expansion is pro-
vided by an active LOW Chip Enable (CE) and three-state driv-
ers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pin will appear on the data output (DOUT)
pin.
The output pin stays in high-impedance state when Chip En-
able (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
256 x 256
ARRAY
C187–1
A12
A13
A14
A15
A0
A1
A2
A3
COLUMN DECODER
INPUT BUFFER
POWER
DOWN
DI
DO
CE
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
19
22
21
20
Top View
DIP
A0
A1
A2
A3
A4
DOUT
WE
GND
CE
VCC
A15
A14
A13
A12
A10
A9
A8
DIN
A11
C187–2
WE
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
A0
A1
A2
A3
A4
NC
CE
VCC
A15
A14
A13
A12
A10
A9
A8
DIN
NC
GND
DOUT
12
13
C187–3
A5
A6
A7
A11
A5
A6
A7
Selection Guide[1]
7C187-15
7C187-20
7C187-25
7C187-35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
90
80
70
70
Maximum Standby Current (mA)
40/20
40/20
20/20
20/20
Note:
1.
For military specifications, see the CY7C187A datasheet.