5 / 9 page
CY7C187
Document #: 38-05044 Rev. **
Page 5 of 9
Read Cycle No. 2[10, 12]
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
50%
50%
DATA VALID
tRC
tACE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZCE
tPD
CE
HIGH
tWC
DATA VALID
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
VCC
SUPPLY
CURRENT
tHZWE
tLZWE
tSD
CE
WE
DATA IN
DATA OUT
ADDRESS
C187–7
C187–8
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
tSD
CE
WE
ADDRESS
DATA IN
DATA OUT
C187–9
Write Cycle No. 1 (WE Controlled)[11]
Write Cycle No. 2 (CE Controlled)[11, 13]
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