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GTL2006PW Datasheet(PDF) 6 Page - NXP Semiconductors |
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GTL2006PW Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 14 page Philips Semiconductors Product data GTL2006 13-bit GTL–/GTL/GTL+ to LVTTL translator 2004 Jun 21 6 Frequently Asked Questions Question 1: On the GTL2006 LVTTL inputs, specifically 10AI1 and 10AI2, when the GTL2006 is unpowered, these inputs may be pulled up to 3.3 V S/B and we want to make sure that there is no leakage path to the power rail under this condition. Are the LVTTL inputs HIGH Impedance when the device is unpowered and will there be any leakage? Answer 1: When the device is unpowered, the LVTTL inputs will be in a high-impedance state and will not leak to VDD if they are pulled high while the device is unpowered. Question 2: Do all the LVTTL inputs have the same unpowered characteristic? Answer 2: Yes. Question 3: What is the condition of the other GTL I/O and LVTTL output pins when the device is unpowered? Answer 3: The open drain outputs, both GTL and LVTTL, will not leak to the power supply if they are pulled high while the device is unpowered. The GTL inputs will also not leak to the power supply under the same conditions. The LVTTL totem pole outputs, however, are not open drain type outputs and there will be current flow on these pins if they are pulled high when VDD is at ground. Question 4: When this sequence occurs: 1) Pin 11BI is driven LOW (at time t0) 2) Pin 11A is driven LOW (at time t1) 3) Pin 11BI stops driving LOW (at time t2) 4)Pin 11A stops driving LOW (at time t3) Are there wired-OR glitches at pin 11BO at time t1 and t2? Answer 4: The output of 11BI is physically wired to the 11A pin. There will be no glitch at t1 when the external driver turns on and drives LOW, unless the external driver is a long distance away and the pull-up is a low value. If the pull-up R = ZO of the line and the current were equally shared, the bounce would be to 1/2 the pull-up voltage, presumably VDD. The input is a 1/2 VDD threshold input, so the glitch may propagate to the 11BO. If the glitch is very short it may not propagate, or if the pull-up were higher the amplitude would be too small to propagate, or if the external driver were sinking more than half of the total current, it would not propagate. If the external driver is weak and a long way away you will most likely see a glitch on 11BO, because there will be a large glitch on 11A. Question 5: Can you give us some guideline on how high the pull-up resistor value at pin 11A needs to be to avoid glitches on 11BO? Answer 5: The 11A pin is a TTL pin, generally the pull-up resistor used on TTL pins are chosen to minimize power rather than to match the line impedance. Most line impedances are in the range of 50 Ω. If the pull-up is 3 × ZO, that is 150 Ω; even if all the current is being sunk by the GTL2006, the initial bounce on 11A would only be 1/3 VDD, and would only last for the round trip time to the external driver, provided that the external driver can sink all of the current, the bounce will return LOW. The 1/3 VDD is not a high level to the GTL2006 11A pin, so no bounce would show up on the 11BO pin. Normal choices for the pull-up on 11A would be in the 1 k Ω to several k Ω range, depending on speed and current considerations. Question 6: Please explain the timing specification of Bn to Bn in the AC Characteristics table. Which specific inputs/outputs does it cover, and why is the H > L transition so slow? Answer 6: The Bn to Bn refers to the 4BI to 7BO1 path and to the 6BI to 7BO2 path. The times are disable and enable times since a LOW on 5BI or 6BI should not be reflected as a LOW on 7BO1 or 7BO2. The tPLH corresponds to the disable time, and the tPHL corresponds to the enable time. The enable time is deliberately slow to prevent glitches/false LOWs on the 7BOn outputs, because a LOW on 5BI drives a LOW on 5A, which is an open-drain I/O and may have a slow rise time. And a LOW on 6BI drives a LOW on 6A that is an open-drain I/O that may also have a slow rise time. Question 6A: Now that I try to examine the circuit from the data sheet, I am just a little bit concerned. Let me try to describe the function first: This circuit is used for monitoring and driving the CPU PROCHOT#. The monitor device is a Heceta7 part and its output is bi-directional, CPU1_PROCHOT# and is connected to 5A. The CPU has an output called PROCHOT#, which goes to 5BI and an input call FRCPROCHOT# that comes from 7BO1. When the CPU is generating PROCHPT# (5BI), we do not want the CPU input FRCPROCHOT# (7BO1) to also see this signal. Scenario 1: CPU driving PROCHOT# – 5BI input is HIGH and goes LOW; output 5A is HIGH and goes LOW following 5BI. The output 7BO should stay HIGH. – 5BI input is LOW and goes HIGH; output 5A is LOW and goes HIGH following 5BI. The output 7BO1 should stay HIGH. Scenario 2: Heceta7 driving CPU1_PROCHOT# – 5A input is HIGH and goes LOW; output 7BO1 is HIGH and goes LOW following 5A. The input 5BI should stay HIGH. – 5A input is LOW and goes HIGH; output 7BO1 is LOW and goes HIGH following 5A. The output 5BI should stay HIGH. Now I can see the reason for the delay in the enable path so that we keep the output disabled to account for the potentially slow riser time on 5A. In my mind, there should also be a delay block shown in the path 5BI to 5A so that the 5BI H-to-L can disable the driver for 7BO1 before the signal appears on the 5A input/output, thus appearing as an input to the driver for 7BO1. Have you characterized what sort of glitch you get on the 7BO1 output on an H-to-L transition on 5BI? Answer 6A: The disable for 7BO1 comes directly from the internal 5BI signal, and by design it always disables the LOW on 7BO1 before the LOW on the 5BI can propagate to the 5AI/O and back to the 7BO1. Question 7: Can I operate the GTL2006 at VTT of 1.2 V and VREF of 0.6 V? Answer 7: Yes; you can operate VTT up to 3.6 V and VREF between 0.5 V to 1.8 V at any VTT to adjust the high and low noise margins to your application. You don’t have to follow the GTL–/GTL/GTL+ specifications. The GTL VIL and VIH will be 50 mV around VREF within the range of 0.5 V to 1.8 V. |
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