HM62256B Series

8

Write Cycle

HM62256B

-5

-7

-8

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

70

—

85

—

ns

Chip selection to end of write

t

CW

40

—

60

—

75

—

ns

5

Address setup time

t

AS

0—

0—

0

—

ns

6

Address valid to end of write

t

AW

40

—

60

—

75

—

ns

Write pulse width

t

WP

35

—

50

—

55

—

ns

4, 13

Write recovery time

t

WR

0—

0—

0

—

ns

7

Write to output in high-Z

t

WHZ

0

20

0

25

0

30

ns

1, 2, 8

Data to write time overlap

t

DW

25

—

30

—

35

—

ns

Data hold from write time

t

DH

0—

0—

0

—

ns

Output active from end of write

t

OW

5—

5—

5

—

ns

2

Output disable to output in High-Z

t

OHZ

0

20

0

25

0

30

ns

1, 2, 8

Notes: 1. t

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. Address must be valid prior to or simultaneously with

CS going low.

4. A write occurs during the overlap of a low

CS and a low WE. A write begins at the latest

transition of

CS going low or WE going low. A write ends at the earliest transition of CS going

high or

WE going high. t

5. t

6. t

7. t

8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite

phase to the outputs must not be applied.

9. If

CS goes low simultaneously with WE going low or after WE going low, the outputs remain in

the high impedance state.

10. Dout is the same phase of the latest written data in this write cycle.

11. Dout is the read data of next address.

12. If

CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the

opposite phase to the outputs must not be applied to them.

13. In the write cycle with

OE low fixed, t

data bus contention.

t