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HY628100B-I Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HY628100B-I Datasheet(HTML) 2 Page - Hynix Semiconductor |
2 / 10 page HY628100B Series Rev 12 / Apr.2001 2 DESCRIPTION The HY628100B is a high speed, low power and 1M bit CMOS Static Random Access Memory organized as 131,072 words by 8bit. The HY628100B uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(L/LL-part) -. 2.0V(min) data retention • Standard pin configuration -. 32pin SOP - 525mil -. 32pin TSOPI - 8X20(Standard) Product Voltage Speed Operation Standby Current(uA) Temperature No (V) (ns) Current/Icc(mA) L LL ( °C) HY628100B 4.5~5.5 50*/55/70/85 10 100 20 0~70 HY628100B-E 4.5~5.5 50*/55/70/85 10 100 30 -25~85 HY628100B-I 4.5~5.5 50*/55/70/85 10 100 30 -40~85 Comment : 50ns is available with 30pF test load. PIN CONNECTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 /WE A13 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss CS2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 A11 A9 A8 A13 /WE CS2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 /CS1 SOP TSOP-I(Standard) PIN DESCRIPTION BLOCK DIAGRAM Pin Name Pin Function /CS1 Chip Select 1 CS2 Chip Select 2 /WE Write Enable /OE Output Enable A0 ~ A16 Address Inputs I/O1 ~ I/O8 Data Inputs / Outputs Vcc Power(4.5V~5.5V) Vss Ground MEMORY ARRAY 128K x 8 ROW DECODER I/O1 I/O8 A0 A16 /CS1 CS2 /OE /WE |
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