Integrated Silicon Solution, Inc. — 1-800-379-4774

1

SR072-1E

05/12/99

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which

may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

• Access time: 45, 70 ns

• Low active power: 200 mW (typical)

• Low standby power

— 250

µW (typical) CMOS standby

— 28 mW (typical) TTL standby

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 5V power supply

DESCRIPTION

The

CMOS static RAM. It is fabricated using

performance, low power CMOS technology.

When

CSis HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down to

250

µW (typical) at CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Select (

CS) input and an active LOW Output Enable (OE)

input. The active LOW Write Enable (

WE) controls both writing

and reading of the memory.

The IS62C256 is pin compatible with other 32K x 8 SRAMs in

plastic SOP or TSOP (Type I) package.

IS62C256

32K x 8 LOW POWER CMOS STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CS

OE

WE

32K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7