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CY7C132/CY7C136
CY7C142/CY7C146
7
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[20, 21]
Read Cycle No. 2 (Either Port-CE/OE)[20, 22]
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
n
Notes:
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = VIL and OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
C132-7
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
C132-8
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
C132-9
tPS
tBLA
tRC
tPWE
VALID
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