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CLC5612IMX Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CLC5612IMX Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 18 page  CLC5612 Dual, High Output, Programmable Gain Buffer General Description The CLC5612 is a dual, low cost, high speed (90MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5612 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1.5mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear phase response up to one half of the −3dB frequency. The CLC5612 offers 0.1dB gain flatness to 18MHz and differential gain and phase errors of 0.15% and 0.02˚. These features are ideal for professional and consumer video applications. The CLC5612 offers superior dynamic performance with a 90MHz small signal bandwidth, 290V/µs slew rate and 6.2ns rise/fall times (2V step). The combination of low quiescent power, high output current drive, and high speed performance make the CLC5612 well suited for many battery powered personal communication/computing sys- tems. The ability to drive low impedance, highly capacitive loads, makes the CLC5612 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5612 will drive a 100 Ω load with only −74/−86dBc second/third harmonic distortion (A V= +2, V OUT =2VPP, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -70/-67dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high resolution A/D converters, the CLC5612 provides excellent −87/−93dBc second/third harmonic distortion (A V = +2, VOUT, f = 1MHz, RL =1kΩ) and fast settling time. Features n 130mA output current n 0.15%, 0.02˚ differential gain, phase n 1.5mA/ch supply current n 90MHz bandwidth (A V = +2) n −87/−93dBc HD2/HD3 (1MHz) n 17ns settling to 0.05% n 290V/µs slew rate n Stable for capacitive loads up to 1000pf n Single 5V to ±5V supplies Applications n Video line driver n Coaxial cable driver n Twisted pair driver n Transformer/coil driver n High capacitive load driver n Portable/battery powered applications n A/D driver Connection Diagram Maximum Output Voltage vs. R L DS015001-1 DS015001-3 Pinout DIP & SOIC January 2001 © 2001 National Semiconductor Corporation DS015001 www.national.com |
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