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SFH6712 Datasheet(PDF) 6 Page - Vishay Siliconix |
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SFH6712 Datasheet(HTML) 6 Page - Vishay Siliconix |
6 / 16 page www.vishay.com 6 Document Number 83683 Rev. 1.3, 27-Apr-04 VISHAY SFH6700/ 01/ 02/ 05/ 11/ 12/ 19 Vishay Semiconductors Coupler 0°C ≤ Tamb ≤ 85 °C; 4.5 V ≤ VCC ≤ 15 V; 1.6 mA ≤ IFon ≤ 5.0 mA; 2.0 ≤ VEH ≤ 15 V; 0 ≤ VEL ≤ 0.8 V; 0 mA ≤ IFoff ≤ 0.1 mA; Typical values: Tamb = 25 °C; VCC = 5.0 V; IFon = 3.0 mA unless otherwise specified Switching Characteristics 0°C ≤ Tamb ≤ 85 °C; 4.5 V ≤ VCC ≤ 15 V; 1.6 mA ≤ IFon ≤ 5.0 mA; 2.0 ≤ VEH ≤ 15 V (SFH6700/19); 0 ≤ VEL ≤ 0.8 V (SFH6700/19); 0 mA ≤ IFoff≤ 0.1 mA Typical values: Tamb = 25 °C; VCC = 5.0 V; IFon = 3.0 mA unless otherwise specified. (3) (3) A 0.1 µF bypass capacitor connected between pins 5 and 8 must be used Typical values: Tamb = 25 °C, VCC = 5.0 V; IFon = 3.0 mA; RL = 390 Ω unless otherwise specified (3) Parameter Test condition Symbol Min Typ. Max Unit Capacitance (input-output) f = 1.0 MHz, pins 1-4 and 5-8 shorted together CIO 0.6 pF Isolation resistance VIO = 500 V, Tamb = 25 °C RIO 1012 Ω VIO = 500 V, Tamb = 100 °C RIO 1011 Ω Parameter Test condition Symbol Min Typ. Max Unit Propagation delay time to logic low output level, SFH6700/01/ 02/11/12/19 Without peaking capacitor tPHL 120 ns With peaking capacitor tPHL 115 300 ns tPLH 125 ns tPLH 90 300 ns Output enable time to logic high (SFH6700/19) tPZH 20 ns Output enable time to logic low (SFH6700/19) tPZL 25 ns Output disable time from logic low (SFH6700/19) tPLZ 50 ns Output rise time 10 % to 90 % tr 40 ns Output fall time 90 % to 10 % tf 10 ns Parameter Test condition Part Symbol Min Typ. Max Unit Propagation delay time to logic low output level Without peaking capacitor SFH6705 tPHL 115 ns With peaking capacitor SFH6705 tPHL 105 300 ns Without peaking capacitor SFH6705 tPLH 125 ns With peaking capacitor SFH6705 tPLH 90 300 ns Output rise time 10 % to 90 % tr 25 ns 90 % to 10 % tr 4ns |
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