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SP8538AS Datasheet(PDF) 6 Page - Sipex Corporation |
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SP8538AS Datasheet(HTML) 6 Page - Sipex Corporation |
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6 / 12 page  SP8538DS/01 SP8538 Micropower Sampling 12-Bit A/D Converter © Copyright 1999 Sipex Corporation 6 1.6 mS 6.25 µA 2.5% The device can be configured such that it delivers serial data MSB first requiring 17 clock periods for a full conversion. Alternately, the device can be programmed to deliver 12 bits of data MSB first, followed by the same 12 bits of data LSB first. This sequence will require 28 clock periods to complete. Please refer to the timing diagram. Circuit Operation The device will ignore any leading zeros applied to the DIN pin even if CS is low. After Chip Select Bar (CS) is brought low and the START bit is clocked in to the converter, the conversion sequence is initiated. Three additional bits are clocked in immediately following the START bit: SGL/DIFF, ODD/ SIGN & MSBF. The second and third bits clocked in determine the MUX configuration (see MUX addressing table). The fourth bit determines the data output format (MSB first or LSB first). Please refer to the timing diagram. The SGL/DIFF bit when zero sets the input MUX for full differential mode and when one, sets the input MUX for single ended mode. The ODD/SIGN bit when zero sets channel zero as the positive input (ground referred for single ended operation and referred to channel one in differential mode). With the ODD/SIGN bit one, channel one will be the positive input (ground referred for single ended operation and referred to channel zero in differential mode). With MSBF set to one, the output data stream will be MSB through LSB, with MSBF set to zero the output data stream will be MSB through LSB followed by the same data in LSB through MSB format. The SP8538 is a SAR converter with full differential multiplexed front end, capacitive DAC, precision comparator, Successive Approximations Register, control logic and data output register. After the input is sampled and held the conversion process begins. The DAC MSB is set and its output is compared with the signal input, if the DAC output is less than the input, the comparator outputs a one which is latched into the SAR and simultaneously made available at the ADC serial output pin. Each bit is tested in a similar manner until the SAR contains a code which represents the signal input to within +1/2 LSB. During this process the SAR content has been shifted out of the ADC serially. If the MSB first format was chosen, the data will appear at the DOUT pin MSB through LSB in 17 clock periods. If the LSB first format was chosen then during conversion the data will appear at the DOUT pin just as before (MSB through LSB) but the LSB will be followed by D1, D2 through the MSB. This sequence will require 28 clock periods. Note that the Chip Select Bar pin must be toggled high between conversions. The DOUT pin will be in a high impedance state whenever Chip Select Bar is high. After Chip Select Bar has been toggled and brought low again, the converter is ready to accept another START bit and begin a new conversion. Full Differential Sampling The SP8538 can be configured for single-ended sampling (i.e. CH0-ground or CH1-ground) or full differential sampling (CH0-CH1 or CH1-CH0). In the full differential sampling configuration, both inputs are sampled and held simultaneously. Because of the balanced differential sampling, dynamic common mode noise riding along the input signal is cancelled above and beyond DC noise. This is a significant improvement over psuedo-differential sampling schemes, where the low side of the input must remain constant during the conversion, and therefore only DC noise (i.e. signal offset) is cancelled. If AC common mode noise is left to be converted along with the differental component, the output signal will be degraded. Full differential sampling allows flexibility in converting the input signal. If the signal low- side is already tied to a ground elsewhere in the system, it can be hardwired to the low side channel (i.e. CH0 or CH1) which acts as a signal ground sense, breaking a potential ground loop. It is also possible to drive the inputs bal- anced differential, as long as both inputs are within the power rails. In this configuration, both the high and low signals have the same impedance looking back to ground, and therefore pick up the same noise along the physical path from signal source (i.e. sensor, transducer, battery) to converter. This noise becomes common mode, and is cancelled out |
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