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CLC935B8C Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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CLC935B8C Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 12 page  http://www.national.com 10 Recommended Output Buffering Circuits In many systems, DSP and other forms of processing will employ TTL or CMOS circuitry. The output logic levels of the CLC935 data converter will need to be translated to match those of the processing circuitry. Several options and translators exist to perform this task. Special care must be used if “10125” type circuits are used since these devices are not particularly suited to a high- resolution, low-noise, analog environment. Other options include TI’s 105574 Latched Translator. ECL to TTL/CMOS Level Translator Options Power Supplies, Grounding, and Bypassing To obtain the best possible performance from any high- speed device, the design engineer must pay close attention to power supplies, grounding and bypassing. This applies not only to the A/D data converter itself but throughout the system as well. The recommended supply decoupling scheme is as follows: One 0.01 µF to 0.033µF chip capacitor at every supply pin, with a +6.8 µF to +10µF tantalum for each of the four main supply feeds (within a few inches of the ADC). Note that supply feeds with excessive digital switching noise may require separate filtering using ferrite beads, additional capacitance, or split supplies. Proper bypassing of all other integrated circuits, especially logic circuits, should minimize power supply and ground transients. All of the CLC935 data converter grounds are internally connected. A single low-impedance ground plane is recommended. Split analog and digital grounds are not recommended. The SIGNAL GND is used internally for the track-and-hold and buffering amplifiers, while the other GROUND pins are essentially power supply returns. The SIGNAL GND pins (pins 39 & 40) are very sensitive nodes, and should have a solid, low-impedance, ground connection. The path that the input signal and its return currents follow must be isolated from other circuitry. Single-point grounding at the data converter should min- imize common impedance paths which would allow other signals to directly couple into the analog input, affecting accuracy. CLC935 Timing Diagram Thermal Considerations The following strategies can be applied to minimize junction temperatures: a) A thick copper ground plane ... an appreciable amount of heat is conducted out of the A/D through its leads. b) A copper or aluminum stand-off between the ground plane and the bottom of the data converter package (thermal paste may be useful). c) A CHO-THERM® pad between the ground plane and the bottom of the data converter package. To maximize heat conduction leave a patch of exposed (no solder mask) ground plane under the data converter. d) Moving air over the A/D converter. e) Heat sink attached to the converter available from National Semiconductor. DATA INV. Optional DATA READY clock generation circuit. Do NOT use CONVERT and CONVERT directly. (MSB) D1 (MSB) D1 D6 D7 (LSB) D12 0.1 µF 0.1 µF CLC935 50 Ω 50 Ω 10114 VBB 100151 100151 * * * * * * ** ** ** ECL PROCESSING CIRCUITRY . . . . . . ** ** Do NOT use terminations * Use standard ECL terminations . . . . . . . . . . . . . . . . . . * ** ** ** ** (MSB) D1 (MSB) D1 D6 D7 (LSB) D12 DATA INV. CLC935 *** *** *** *** *** SN10KHT5574 SN10KHT5574 TTL PROCESSING CIRCUITRY DATA READY DATA READY *** Follow mfg. recomendations ** Do NOT use terminations * Use standard ECL terminations Effective Aperature Delay Analog Input Sample N Sample N + 1 Sample N + 2 Sample N + 3 CONVERT CONVERT Data Output N - 2 N - 3 N - 1 N - 2 N CLC935 N - 1 N + 1 N tPWL tPWH tHLD tDIV 1 CR Note: tDIV = tHLD + Data Bit Skew |
Similar Part No. - CLC935B8C |
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Similar Description - CLC935B8C |
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