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AK4497EQ Datasheet(PDF) 7 Page - Asahi Kasei Microsystems |
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AK4497EQ Datasheet(HTML) 7 Page - Asahi Kasei Microsystems |
7 / 98 page [AK4497] Rev. 0.1 2015/11 - 7 - No. Pin Name I/O Function 19 TDM0 I TDM Mode select pin in Parallel control mode. DCLK I DSD clock Pin in DSD Mode (DSDPATH bit = “0”) 20 TDM1 I TDM Mode select pin in Parallel control mode. 21 DCHAIN I Daisy Chain Mode select pin in Parallel control mode. 22 INVR I Rch output data invert enable pin in Parallel control mode. 23 TESTE I Testmode Enable pin. (Internal pull-down pin) 24-26 VREFHR I Rch High Level Voltage Reference Input Pin 27-29 VREFLR I Rch Low Level Voltage Reference Input Pin 30 VCMR I Right channel Common Voltage Pin, Normally connected to VREFLR with a 10uF electrolytic cap. 31,32 AOUTRN O Rch Negative Analog Output Pin 33,34 AOUTRP O Rch Positive Analog Output Pin 35-37 VDDR - Rch Analog Power Supply Pin 38-40 VSSR - Analog Ground Pin 41-43 VSSL - Analog Ground Pin 44-46 VDDL - Lch Analog Power Supply Pin . 47,48 AOUTLP O Lch Positive Analog Output Pin 49,50 AOUTLN O Lch Negative Analog Output Pin 51 VCML - Left channel Common Voltage Pin Normally connected to VREFLL with a 10uF electrolytic cap. 52-54 VREFLL I Lch Low Level Voltage Reference Input Pin 55-57 VREFHL I Lch High Level Voltage Reference Input Pin 58 EXTR I External Resistor Connect Pin Rext=33kΩ(±1%) toAVSS 59 AVDD - (LDOE pin = “H”) Analog Power Supply Pin, 3.0 3.6V - (LDOE pin = “L”) Analog Power Supply Pin, 1.7 3.6V 60 AVSS - Analog Ground Pin 61 MCLK I Master Clock Input Pin 62 DVDD O (LDOE p in = “H”) LDO Output Pin, This pin should be connected to DVSS with 1.0µF. - (LDOE pin = “L”) Digital Power Supply Pin, 1.7 1.98V 63 DVSS - Digital Ground Pin 64 TVDD - (LDOE pin = “H”) Digital Power Supply Pin, 3.0 3.6V - (LDOE pin = “L”) Digital Power Supply Pin, 1.7 3.6V Note 1. All input pins except internal pull-up/down pins must not be left floating. Note 2. The AK4497 must be reset by PDN pin after changing Parallel/Serial mode by the PSN pin. Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings. |
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