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AS7C256-15PC Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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AS7C256-15PC Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 8 page AS7C256 AS7C256L 6 1. During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2. This parameter is sampled and not 100% tested. 3. For test conditions, see AC Test Conditions, Figures A, B, C. 4. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage. 5. This parameter is guaranteed but not tested. 6. WE is HIGH for read cycle. 7. CE and OE are LOW for read cycle. 8. Address valid prior to or coincident with CE transition LOW. 9. All read cycle timings are referenced from the last valid address to the first transitioning address. 10. CE or WE must be HIGH during address transitions. 11. All write cycle timings are referenced from the last valid address to the first transitioning address. Parameter Symbol Test Conditions Min Max Unit VCC for Data Retention VDR VCC = 2.0V CE ≥ V CC–0.2V Vin ≥ VCC–0.2V or Vin ≤ 0.2V 2.0 – V Data Retention Current ICCDR – 150 µA Chip Enable to Data Retention Time tCDR 0– ns Operation Recovery Time tR tRC –ns Input Leakage Current | I LI | –1 µA DATA RETENTION CHARACTERISTICS (L Version Only) DATA RETENTION WAVEFORM (L Version Only) VCC CE tR tCDR Data retention mode 4.5V 4.5V VDR ≥ 2.0V VIH VIH VDR AS7C256-07 AC TEST CONDITIONS 255 Ω – Output load: see Figure B, except for tCLZ and tCHZ see Figure C. – Input pulse level: GND to 3.0V. See Figure A. – Input rise and fall times: 5 ns. See Figure A. – Input and output timing reference levels: 1.5V. 5 pF* 480 Ω Dout GND +5V 168 Ω Thevenin Equivalent: Dout +1.728V Figure C: Output Load for tCLZ, tCHZ 255 Ω 30 pF* 480 Ω Dout GND +5V Figure B: Output Load *including scope 10% 90% 10% 90% GND +3.0V Figure A: Input Waveform and jig capacitance AS7C256-08 AS7C256-09 AS7C256-10 NOTES |
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