IS61LV256

2-4

Integrated Silicon Solution, Inc.

Rev. F 0296

SR81995LV61

AC TEST LOADS

635

Ω

30 pF

Including

jig and

scope

702

Ω

OUTPUT

3.3V

635

Ω

5 pF

Including

jig and

scope

702

Ω

OUTPUT

3.3V

Figure 1a.

Figure 1b.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels

Output Load

See Figures 1a and 1b

-12 ns

-15 ns

-20 ns

-25 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

12

—

15

—

20

—

25

—

ns

Address Access Time

—

12

—

15

—

20

—

25

ns

Output Hold Time

2

—

2

—

2

—

2

—

ns

CE Access Time

—

12

—

15

—

20

—

25

ns

OE Access Time

—

6

—

7

—

8

—

9

ns

OE to Low-Z Output

0

—

0

—

0

—

0

—

ns

OE to High-Z Output

—

7

—

8

—

9

—

10

ns

CE to Low-Z Output

3

—

3

—

3

—

3

—

ns

CE to High-Z Output

—

5

—

6

—

9

—

10

ns

CE to Power-Up

0

—

0

—

0

—

0

—

ns

CE to Power-Down

—

13

—

15

—

18

—

20

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured

±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.