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AD1836AS Datasheet(PDF) 7 Page - Analog Devices |
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AD1836AS Datasheet(HTML) 7 Page - Analog Devices |
7 / 18 page PRELIMINARY TECHNICAL DATA REV. PrC AD1836 –7– PIN FUNCTION DESCRIPTIONS PIN No. Mnemonic In/Out Description 1, 40 DVDD I Digital Power Supply. Connect to digital 5 V supply. 2 CDATA I Serial Control Input 3 PD/RST I Power-Down Reset 4 OUTLP3 O DAC 3 (Left) Positive Output 5 OUTLN3 O DAC 3 (Left) Negative Output 6 OUTLP2 O DAC 2 (Left) Positive Output 7 OUTLN2 O DAC 2 (Left) Negative Output 8 OUTLP1 O DAC 1 (Left) Positive Output 9 OUTLN1 O DAC 1 (Left) Negative Output 10, 15 AVDD I Analog Power Supply. Connect to analog 5 V. 11, 14, 28, 29 AGND I Analog Ground 12 FILTD I Filter Capacitor Connection. Recommend 10 µF//100 nF. 13 FILTR I Voltage Reference Filter Capacitor Connection. Recommend 10 µF//100 nF. 16 ADC1INLP I ADC1 Left Positive Input 17 ADC1INLN I ADC1 Left Negative Input 18 ADC1INRP I ADC1 Right Positive Input 19 ADC1INRN I ADC1 Right Negative Input 20 ADC2INL+/CAPL2 I ADC2 Left Positive Input (Direct Mode)/ADC2 Left Decoupling Cap (MUX/PGA and PGA Differential Mode) 21 ADC2INL–/CAPL1 I ADC2 Left Negative Input (Direct Mode)/ADC2 Left Decoupling Cap (MUX/PGA and PGA Differential Mode) 22 ADC2INL1 I ADC2 Left Input 2 (MUX/PGA Mode)/Left Positive Input (PGA Differ- ential Mode) 23 ADC2INL2 I ADC2 Left Input 1 (MUX/PGA Mode)/Left Negative Input (PGA Differ- ential Mode) 24 ADC2INR2 I ADC2 Right Input 1 (MUX/PGA Mode)/Right Negative Input (PGA Differential Mode) 25 ADC2INR1 I ADC2 Right Input 2 (MUX/PGA Mode)/Right Positive Input (PGA Differential Mode) 26 ADC2INR–/CAPR1 I ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Cap (MUX/PGA and PGA Differential Mode) 27 ADC2INR+/CAPR2 I ADC2 Right Positive Input (Direct Mode)/ADC2 Right Decoupling Cap (MUX/PGA and PGA Differential Mode) 30 OUTRN1 O DAC 1 (Right) Negative Output 31 OUTRP1 O DAC 1 (Right) Positive Output 32 OUTRN2 O DAC 2 (Right) Negative Output 33 OUTRP2 O DAC 2 (Right) Positive Output 34 OUTRN3 O DAC 3 (Right) Negative Output 35 OUTRP3 O DAC 3 (Right) Positive Output 36 DLRCLK I/O LR Clock for DACs 37 DBCLK I/O Bit Clock for DACs 38 DSDATA1 I DAC Input #1 (Input to DAC1 and DAC2) 39, 52 DGND I Digital Ground 41 DSDATA2 I DAC Input #2 (Input to DAC3 and DAC4) 42 DSDATA3 I DAC Input #3 (Input to DAC5 and DAC6) 43 ABCLK O Bit Clock for ADCs 44 ALRCLK O LR Clock for ADCs 45 MCLK I Master Clock Input 46 ODVDD I Digital Output Driver Power Supply 47 ASDATA1 O ADC Serial Data Output #1 48 ASDATA2 O ADC Serial Data Output #2 49 COUT O Output for Control Data 50 CLATCH I Latch Input for Control Data 51 CCLK I Control Clock Input for Control Data 52 DGND I Digital Ground |
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