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ADS1244IDGSR Datasheet(PDF) 10 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part # ADS1244IDGSR
Description  Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

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ADS1244
10
SBAS273
www.ti.com
POWER-UP
Self-calibration is performed at power-up to minimize offset and
gain errors. In order for the self-calibration at power-up to work
properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t1, as shown in Figure 11.
SCLK must be held LOW during this time. Once calibration is
complete, DRDY/DOUT will go LOW indicating data is ready
for retrieval. The time required before the first data is ready (t6)
depends on how fast AVDD and DVDD ramp to their final value
(t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz).
If the system environment is not stable during power-up (the
temperature is varying or the supply voltages are moving
around), it is recommended that a self-calibration be issued
after everything is stable.
DATA FORMAT
The ADS1244 outputs 24 bits of data in Binary Two’s
Complement format. The Least Significant Bit (LSB) has a
weight of (2VREF)/(223 – 1). A positive full-scale input pro-
FIGURE 11. Power-Up Timing.
AVDD and DVDD
DRDY/DOUT
SCLK
t
1
t
2
Data ready after power-up calibration.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t1(1)
AVDD and DVDD settling time.
100
ms
t2(1)
Wait time for calibration and first data conversion.
316
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional
to CLK period.
duces an output code of 7FFFFFH and the negative full-scale
input produces an output code of 800000H. The output clips
at these codes for signals exceeding full-scale. Table I
summarizes the ideal output codes for different input signals.
INPUT SIGNAL VIN (AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ +2V
REF
7FFFFFH
+
2
21
23
VREF
000001H
0
000000H
2
21
23
VREF
FFFFFFH
≤−


2
2
21
23
23
VREF
800000H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
TABLE I. Ideal Output Code versus Input Signal.


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