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AM24LC08ISA Datasheet(PDF) 6 Page - Anachip Corp

Part # AM24LC08ISA
Description  2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM
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Manufacturer  ANACHIP [Anachip Corp]
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AM24LC08ISA Datasheet(HTML) 6 Page - Anachip Corp

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2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM
AM24LC08
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
6/10
ATC
Write Operations (Continued)
Current Address Read
The AM24LC08 contains an address counter that
maintains the address of the last accessed word,
internally incremented by one. Therefore if the
previous access (either a read or write operation )
was to address n, the next current address read
operation would access data from address n + 1.
Upon receipt of the slave address with R/W bit set to
one, the AM24LC08 issues an acknowledge and
transmits the eight bit data word. The master will not
acknowledge the transfer but does generate a stop
condition
and
the
AM24LC08
discontinues
transmission. (Shown in Figure 6)
Random Read
Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, first the word
address must be set. This is done by sending the
word address to the AM24LC08 as part of a write
operation. After the word address is sent, the master
generates
a
start
condition
following
the
acknowledge. This terminates the write operation,
but not before the internal address pointer is set.
Then the master issues the control byte again but
with R/W bit set to a one. The AM24LC08 will then
issue an acknowledge and transmit the eight bit data
word. The master will not acknowledge the transfer
but does generate a stop condition and the
AM24LC08 discontinues transmission. (Shown in
Figure 7)
Sequential Read
Sequential reads are initiated by either a current
address read or a random read. After the master
receives a data word, it responds with an
acknowledge. As long as the E
2PROM receives an
acknowledge, it will continue to increment the data
words. When the memory address limit is reached,
the data word address will “roll over” and the
sequential read will continue. The sequential read
operation is terminated when the master does not
respond with a zero but does generate a following
stop condition.


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