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COP87L84CLN-XE Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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COP87L84CLN-XE Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 34 page  Timers The device contains a very versatile set of timers (T0 T1 T2) All timers and associated autoreloadcapture registers power up containing random data TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode This IDLE mode support is furnished by the IDLE timer T0 which is a 16-bit timer The Timer T0 runs continuously at the fixed rate of the instruction cycle clock tc The user cannot read or write to the IDLE Timer T0 which is a count down timer The Timer T0 supports the following functions Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode The IDLE Timer T0 can generate an interrupt when the thir- teenth bit toggles This toggle is latched into the T0PND pending flag and will occur every 4 ms at the maximum clock frequency (tc e 1 ms) A control flag T0EN allows the interrupt from the thirteenth bit of Timer T0 to be enabled or disabled Setting T0EN will enable the interrupt while reset- ting it will disable the interrupt TIMER T1 AND TIMER T2 The device has a set of two powerful timercounter blocks T1 and T2 The associated features and functioning of a timer block are described by referring to the timer block Tx Since the two timer blocks T1 and T2 are identical all com- ments are equally applicable to either timer block Each timer block consists of a 16-bit timer Tx and two supporting 16-bit autoreloadcapture registers RxA and RxB Each timer block has two pins associated with it TxA and TxB The pin TxA supports IO required by the timer block while the pin TxB is an input to the timer block The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead The timer block has three operating modes Processor Inde- pendent PWM mode External Event Counter mode and Input Capture mode The control bits TxC3 TxC2 and TxC1 allow selection of the different modes of operation Mode 1 Processor Independent PWM Mode As the name suggests this mode allows the device to gen- erate a PWM signal with very minimal user intervention The user only has to define the parameters of the PWM signal (ON time and OFF time) Once begun the timer block will continuously generate the PWM signal completely inde- pendent of the microcontroller The user software services the timer block only when the PWM parameters require up- dating In this mode the timer Tx counts down at a fixed rate of tc Upon every underflow the timer is alternately reloaded with the contents of supporting registers RxA and RxB The very first underflow of the timer causes the timer to reload from the register RxA Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB The Tx Timer control bits TxC3 TxC2 and TxC1 set up the timer for PWM mode operation Figure 6 shows a block diagram of the timer in PWM mode TLDD12524 – 9 FIGURE 6 Timer in PWM Mode The underflows can be programmed to toggle the TxA out- put pin The underflows can also be programmed to gener- ate interrupts Underflows from the timer are alternately latched into two pending flags TxPNDA and TxPNDB The user must reset these pending flags under software control Two control en- able flags TxENA and TxENB allow the interrupts from the timer underflow to be enabled or disabled Setting the timer enable flag TxENA will cause an interrupt when a timer un- derflow causes the RxA register to be reloaded into the tim- er Setting the timer enable flag TxENB will cause an inter- rupt when a timer underflow causes the RxB register to be reloaded into the timer Resetting the timer enable flags will disable the associated interrupts Either or both of the timer underflow interrupts may be en- abled This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output Alternatively the user may choose to interrupt on both edges of the PWM output Mode 2 External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above The main difference is that the timer Tx is clocked by the input signal from the TxA pin The Tx timer control bits TxC3 TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin Underflows from the timer are latched into the TxPNDA pending flag Setting the TxENA control flag will cause an interrupt when the timer underflows In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB control flag is set The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag Figure 7 shows a block diagram of the timer in External Event Counter mode Note The PWM output is not available in this mode since the TxA pin is being used as the counter input clock http www nationalcom 10 |
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