COP87L89RB datasheet(6/72 Pages) NSC

Part #	COP87L89RB

Description	8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

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Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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DC Electrical Characteristics (Continued)

Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at VCC or GND, and outputs open.

Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to VCC; Port C, G, E, F, L, M and N I/Os con-

figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will

pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.

Note 5: . HALT and IDLE current specifications assume CAN block comparators are disabled.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current

to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

Note 7: Condition and parameter valid only for part in HALT mode.

Note 8: Parameter characterized but not tested.

AC Electrical Characteristics

−40˚C

≤ T

A ≤ +85˚C

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

c)

Crystal/Resonator

V

CC ≥ 4.5V

1.0

DC

µs

Inputs

t

SETUP

V

CC ≥ 4.5V

200

ns

t

HOLD

V

CC ≥ 4.5V

60

ns

Output Propagation Delay (t

PD1,tPD0) (Note 9)

C

L = 100 pF, RL = 2.2 kΩ

SK, SO

V

CC ≥ 4.5V

0.7

µs

All others

V

CC ≥ 4.5V

1

µs

MICROWIRE

Setup Time (tUWS) (Note 10)

20

ns

Hold Time (tUWH) (Note 10)

56

ns

Output Pop Delay (tUPD)

220

ns

Input Pulse Width

Interrupt High Time

1

t

c

Interrupt Low Time

1t

c

Timer 1, 2 High Time

1

t

c

Timer 1, 2 Low Time

1

t

c

Reset Pulse Width (Note 10)

1.0

µs

tc = Instruction Cycle Time

The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can support a bus

speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred on the

bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum of 125k

bits/s with eight byte messages and a 10 MHz oscillator.

For device testing purpose of all AC parameters, VOH will be tested at 0.5*VCC.

Note 9: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 10: Parameter not tested.

On-Chip Voltage Reference

−40˚C

≤ T

A ≤ +85˚C

Parameter

Conditions

Min

Max

Units

Reference Voltage

I

OUT < 80 µA,

0.5V

CC −0.12

0.5V

CC +0.12

V

REF

V

CC =5V

Reference Supply

I

OUT = 0A, (No Load)

120

µA

Current, I

DD

V

CC = 5V (Note 11)

Note 11: Reference supply IDD is supplied for information purposes only, it is not tested.

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COP87L89RB Datasheet(PDF) 6 Page - National Semiconductor (TI)

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